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Digital frequency divider

  • Selectable division word size in verilog definition

Pins

Name Description Type Direction Vmin Vmax
in TBD signal input -0.5 VDD + 0.3
reset TBD signal input -0.5 VDD + 0.3
out TBD signal output -0.5 VDD + 0.3

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area µm²
width µm
height µm
DRC_errors
LVS_errors

Figure(s)

frequency_divider_symbol.svg

Figure 1

Summary

Catalog ID

FREQUENCY_DIVIDER

IP Provider

community

Designer

efabless engineering

Type

Hard IP

Node

180nm

Vendor

efabless

Foundry

X-FAB

Process

EFXH018C

Category

Oscillator and Clocking

Certifications

N/A

Licensing

Info

Contact Designer

Maturity

Stage

layout

# of Tries

15

Library Package

Version

1.0

Version Date

May 29, 2018