Summary

SK-EDP1.4B-RECV
design house
Sankalp
Hard IP
80nm
Sankalp
UMC
UMC 80nm
Display Port

Licensing

Contact Designer

Maturity

product
0

Library Package

1.0
Oct 01, 2018

Certifications

icon Vendor Certified

Description

The low power embedded display port PHY has been developed for eDP-TCON SoCs to be used for Chip on Glass (COG) applications at speeds up to 2.7 Gb/s data rates. The robust design is capable to withstand 120 mV voltage drop and 100 mV pk-pk power supply noise typically seen on COG applications. Programmable receiver equalization adaptively corrects the signal distortions caused in eDP cable and connector assembly. Built in self-test features offer at speed testing for mass production, functional and performance diagnostics as well as silicon characterization in the lab. The PHY is designed for UMCs 80nm CMOS process and uses only five metal layers.

Features

  • eDP1.4b receiver for eDP-TCON SoC
  • 20 mA/ lane current consumption
  • Single Vdd @ 1.2 Volt typical
  • Data Rates: 1.6, 2.16, 2.43, 2.7 Gb/s
  • Designed for Chip on Glass app
  • On chip at speed BIST for mass production and diagnostics
  • Dual Poly 5 level metal process in UMC 80 nm
  • Full link , Fast link and no link training modes of operation
  • Single, dual or 4 lane operation with power saving modes
  • Low speed functions designed in soft logic for easier integration into SoC