This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-64 input clock divider, a 1-128 feedback clock divider and a 1-8 output clock divider. By setting PLL_DM, PLL_DN and PLL_DP to different values, the output clock will be locked at different multiples of the input frequency.

Features

• Process: GLOBALFOUNDRIES 0.13um 1.2v 1P6M/7M/8M CMOS logic process
• Supply voltage: 1.08V~1.2V~1.32V
• Current: <2.5mA
• Operating junction temperature: - 40°C ~ +25°C ~ +125°C
• Core area: 541.73um x 438.75um
• Two outputs:
  - PLL_CLKO: standard output from the output divider
  - PLL_CLK: output from VCO directly