Summary

VS_GF13V33_ADC_08C
Vendor
VeriSilicon
Hard IP
130nm
VeriSilicon
GlobalFoundries
GF013GA
Simulation Model

Licensing

N/A
N/A

Maturity

layout
1

Library Package

1.0
Oct 14, 2011

Certifications

icon Vendor Certified

Description

This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core internal SAR ADC, 8-1 MUX and touch screen drivers. The internal SAR ADC includes sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.

External reference or internal reference is needed. In addition, the reference voltage input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bits of resolution. The ADC has dual speed modes – 1M or 200K - working in 200K mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The ADC is especially suitable to act as Touch Screen Controller, demanding less off-chip components to complete the design.

Battery voltage detection could be easily accomplished by the SAR ADC. It has in-chip resistor divider and keypad interrupt signal generator. The converter has flexible control logic, and could be easily embedded in a complex system. It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.

Features

  • 12-bit resolution
  • 1M or 200K sample per sec modes