The aadcc03_1v8 cell is a 12-bit fully differential successive approximation Analog-to-Digital converter (ADC) based on a high-resolution 12-bit segmented capacitor digital-to-analog converter (DAC) decreasing the total input capacitance. Its typical conversion rate is 1.25 MSPS. It requires 1.8V power supply and the additional external reference voltage.
There is an option of using an external current source or internal current source with trimming mode. Trimming of the internal current source allows selecting optimal current. At typical clock frequencies, it is recommended to use typical current mode. At clock frequencies of 40 MHz and higher, in order to improve the performance of the ADC, it is recommended to increase current, not exceeding the maximum allowable value.
• APB compatible
• Integrated biasing / external biasing choice
• Trimming mode of internal biasing
• Physical size (h x w): 512.165 μm x 524.825 μm (macro cell)
• XH018, LPMOS, ISOMOS, MET3, METMID, MIM, MRPOLY modules
Aug 05, 2017