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Two power supply domains

– 1.8 V and 3.3 V power supply for read, write, store and recall

I/O Configuration

– Separate input and output data buses

– Signal driven read access from EEPROM

– Signal driven write access to EEPROM

– Signal driven store access to EEPROM

– Signal driven recall access from EEPROM

Options

– On-chip charge pump

– 2 separate controllable non-volatile memory parts (page 1 and page 2)

– External clock of 4 MHz 10% (outside of specified IP) is required for controlling non-volatile access.

Serial Port

– DWSP (Diagnostic Wrapper Serial Port)

– Supports reduced IEEE P1500 standard (e.g. No bypass functionality).

– Allows access to NVRAM only or to all NVRAM connected to the same serial chain.

Endurance / Data Retention

– Minimum 100000 store cycles to EEPROM 25 °C

– Minimum 10000 store cycles to EEPROM 125 °C

– Minimum 10000 store cycles to EEPROM 150 °C

– Minimum 1000 store cycles to EEPROM 175 °C

– Minimum 20 years data retention 125 °C (w/wo cycles)

– Minimum 6 years data retention 150 °C (w/wo cycles)

– Minimum 2 years data retention 175 °C (w/wo cycles)

Power Consumption

– Zero static DC power consumption (intrinsic leakage only)

  • 128x32 bit words 
  • 7-bit address
  • Typical cycle time 12.85 ns
  • Worse case cycle time 22.46 ns
  • Power consumption, read 45.29 mW/MHz
  • Power consumption, write 54.82 mW/MHz
  • Typical access time 11.14 ns
  • Height = 254.6 um
  • Length = 408.86 um
  • Area = 0.104 mm2

Pins

Name Description Type Direction Vmin Vmax
CLK memory clock input 4MHz signal input -0.5 VDD18M + 0.3
CLKI symmetric clock to charge pump signal output -0.5 VDD18M + 0.3
CLK4 test clock input signal input -0.5 VDD18M + 0.3
TM_NVCP[3:0] test mode input digital input -0.5 VDD18M + 0.3
TM_NVCPI[3:0] test mode output digital output -0.5 VDD18M + 0.3
PEIN test mode signal digital input -0.5 VDD18M + 0.3
RDY ready signal signal output -0.5 VDD18M + 0.3
VSE1 page 1 store voltage signal input -10.8 +12.2
VSE2 page 2 store voltage signal input -10.8 +12.2
MEM_ALLC memory select digital input -0.5 VDD18M + 0.3
MEM_SEL memory page select digital input -0.5 VDD18M + 0.3
CE chip enable digital input -0.5 VDD18M + 0.3
WE write enable digital input -0.5 VDD18M + 0.3
HR hardware recall digital input -0.5 VDD18M + 0.3
HS hardware store digital input -0.5 VDD18M + 0.3
RCLT recall access state digital output -0.5 VDD18M + 0.3
MEM1_ENT page 1 voltage enable digital output -0.5 VDD18M + 0.3
MEM2_ENT page 2 voltage enable digital output -0.5 VDD18M + 0.3
TRIM[15:0] oscillator trim digital input -0.5 VDD18M + 0.3
VSESTART start store access digital output -0.5 VDD18M + 0.3
POR power on reset digital input -0.5 VDD18M + 0.3
VSEBUSY charge pump state digital input -0.5 VDD18M + 0.3
BUSYNVC charge pump state digital output -0.5 VDD18M + 0.3
A[6:0] Memory address bus (7 bits) digital input -0.5 VDD18M + 0.3
DOUT[31:0] Memory data output (8 bits) digital output -0.5 VDD18M + 0.3
DIN[31:0] Memory data input (32 bits) digital input -0.5 VDD18M + 0.3
VCORE Core power supply signal inout VDD33M 5.0
VDD18M Digital power supply power inout 1.62 1.98
VDD33M Analog power supply power inout 3.63 2.97
VSSM Digital Ground ground inout 0 0

Global Conditions

Name Typical Minimum Maximum Units
VDD18M 1.8 V
VDD33M 3.3 V
Ground 0 V

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area µm²
width µm
height µm
DRC_errors
LVS_errors

Figure(s)

XNVR_128X32P64_VD01_symbol.svg

Figure 1

Summary

Catalog ID

XNVR_128X32P64_VD01

IP Provider

foundry

Designer

X-FAB

Type

Hard IP

Node

180nm

Vendor

X-FAB

Foundry

X-FAB

Process

EFXH018D

Category

N/A

Certifications

icon icon

Licensing

Info

Contact Designer

Maturity

Stage

schematic

# of Tries

4

Library Package

Version

3.0

Version Date

Apr 09, 2019