CARAVEL USER PROJECT
This repo contains a sample user project that utilizes the caravel chip user space. The user project is a simple counter that showcases how to make use of caravel's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw shuttle projects.
Caravel is a template SoC for Google SKY130 free shuttles. The current SoC architecture is given below.
Datasheet and detailed documentation exist here
Caravel is composed of three main sub-blocks: management area, storage area, and user project area.
The managment area includes a picorv32 based SoC that includes a number of periphrals like timers, uart, and gpio. The managemnt area runs firmware that can be used to:
- Configure User Project I/O pads
- Observe and control User Project signals (through on-chip logic analyzer probes)
- Control the User Project power supply
For a complete list of the SoC periphrals, check the memory map
The storage area is an auxiliary storage space for the managment SoC. It holds two dual port RAM blocks (1KB) generated by OpenRAM
The storage area is only accessible by the management SoC.
User Project Area
This is the user space. It has a limited silicon area
2.92mm x 3.52mm as well as a fixed number of I/O pads
38 and power pads
The user space has access to the following utilities provided by the management SoC:
128Logic analyzer probes
- Wishbone port connection to the management SoC wishbone bus.
Quick Start for User Projects
Your area is the full user space, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the
user_project_wrapper for digital projects or insert it into
user_project_analog_wrapper for analog projects.
Digital User Project
If you are building a digital project for the user space, check a sample project at caravel_user_project.
If you will use OpenLANE to harden your design, go through the instructions in this README.
Digital user projects should adhere the following requirements:
- Top module is named
user_project_wrapperadheres to the pin order defined at Digital Wrapper Pin Order.
user_project_wrapperadheres to the fixed design configurations at Digital Wrapper Fixed Configuration.
- The user project repository adheres to the Required Directory Structure.
Analog User Project
If you are building an analog project for the user space, check a sample project at caravel_user_project_analog.
Analog user projects should adhere the following requirements:
- Top module is named
user_analog_project_wrapperuses the empty analog wrapper.
user_analog_project_wrapperadheres to the same pin order and placement of the empty analog wrapper.
Please make sure to run
make compress before commiting anything to your repository. Avoid having 2 versions of the
gds/user_project_wrapper.gds one compressed and the other not compressed.
For information on tooling and versioning, please refer to tool-versioning.rst.
Required Directory Structure
gds/: includes all the gds files used or produced from the project.
def: includes all the def files used or produced from the project.
lef/: includes all the lef files used or produced from the project.
mag/: includes all the mag files used or produced from the project.
maglef: includes all the maglef files used or produced from the project.
spi/lvs/: includes all the spice files used or produced from the project.
verilog/dv: includes all the simulation test benches and how to run them.
verilog/gl/: includes all the synthesized/elaborated netlists.
verilog/rtl: includes all the Verilog RTLs and source files.
openlane/<macro>/: includes all configuration files used to run openlane on your project.
info.yaml: includes all the info required in this example. Please make sure that you are pointing to an elaborated caravel netlist as well as a synthesized gate-level-netlist for the user_project_wrapper
If you're using openlane to harden your design, the
maglefdirectories should be automatically populated by openlane.
- SKY130 Open PDK
- 37 programable IO's
- 10 sq mm user design space