Summary

RAVENNA
N/A
efabless engineering
Hard IP
180nm
efabless
X-FAB
EFXH018D

Licensing

Contact Designer

Maturity

layout
34

Library Package

4.0
Aug 13, 2019

Certifications

Description

Full-chip implementation of the PicoRV32 PicoSoC in X-Fab XH018. The ravenna chip contains 8kB memory, 512 bits non-volatile memory, an I2C master, two ADCs, a DAC, comparator, bandgap, RC oscillator, and over-temperature alarm, as well as 16 bits of general-purpose digital inputs/outputs. It is powered off of a single 3.3V supply and driven by a 5 to 12 MHz crystal. The core CPU clock speed is 8 times the crystal frequency.

 

Features

  • 8kB memory
  • 512 bits non-volatile memory
  • 2 10-bit ADCs
  • 1 10-bit DAC
  • I2C controller
  • QSPI flash controller
  • UART

Figure(s)


Pins

NAME DESCRIPTION TYPE DIRECTION VMIN VMAX
XCLK external 1-pin clock input signal input -0.5 VDD3V3 + 0.3
XI crytal oscillator input signal inout -0.5 VDD3V3 + 0.3
XO crytal oscillator output signal inout -0.5 VDD3V3 + 0.3
SDI housekeeping SPI data input signal input -0.5 VDD3V3 + 0.3
SDO housekeeping SPI data output signal output -0.5 VDD3V3 + 0.3
SCK housekeeping SPI clock signal input -0.5 VDD3V3 + 0.3
CSB housekeeping SPI chip select (sense inverted) signal input -0.5 VDD3V3 + 0.3
ser_rx UART receive channel signal input -0.5 VDD3V3 + 0.3
ser_tx UART transmit channel signal output -0.5 VDD3V3 + 0.3
i2c_sda I2C data channel signal inout -0.5 VDD3V3 + 0.3
i2c_scl I2C clock channel signal inout -0.5 VDD3V3 + 0.3
spi_sck SPI master clock signal output -0.5 VDD3V3 + 0.3
spi_csb SPI master select signal output -0.5 VDD3V3 + 0.3
spi_sdo SPI master data output signal output -0.5 VDD3V3 + 0.3
spi_sdi SPI master data input signal input -0.5 VDD3V3 + 0.3
irq Dedicated external interrupt signal input -0.5 VDD3V3 + 0.3
flash_csb Flash SPI chip select (active low) signal output -0.5 VDD3V3 + 0.3
flash_clk Flash SPI clock signal output -0.5 VDD3V3 + 0.3
flash_io0 Flash QSPI channel 0 signal inout -0.5 VDD3V3 + 0.3
flash_io1 Flash QSPI channel 1 signal inout -0.5 VDD3V3 + 0.3
flash_io2 Flash QSPI channel 2 signal inout -0.5 VDD3V3 + 0.3
flash_io3 Flash QSPI channel 3 signal inout -0.5 VDD3V3 + 0.3
gpio_15 GPIO channel 15 signal inout -0.5 VDD3V3 + 0.3
gpio_14 GPIO channel 14 signal inout -0.5 VDD3V3 + 0.3
gpio_13 GPIO channel 13 signal inout -0.5 VDD3V3 + 0.3
gpio_12 GPIO channel 12 signal inout -0.5 VDD3V3 + 0.3
gpio_11 GPIO channel 11 signal inout -0.5 VDD3V3 + 0.3
gpio_10 GPIO channel 10 signal inout -0.5 VDD3V3 + 0.3
gpio_9 GPIO channel 9 signal inout -0.5 VDD3V3 + 0.3
gpio_8 GPIO channel 8 signal inout -0.5 VDD3V3 + 0.3
gpio_7 GPIO channel 7 signal inout -0.5 VDD3V3 + 0.3
gpio_6 GPIO channel 6 signal inout -0.5 VDD3V3 + 0.3
gpio_5 GPIO channel 5 signal inout -0.5 VDD3V3 + 0.3
gpio_4 GPIO channel 4 signal inout -0.5 VDD3V3 + 0.3
gpio_3 GPIO channel 3 signal inout -0.5 VDD3V3 + 0.3
gpio_2 GPIO channel 2 signal inout -0.5 VDD3V3 + 0.3
gpio_1 GPIO channel 1 signal inout -0.5 VDD3V3 + 0.3
gpio_0 GPIO channel 0 signal inout -0.5 VDD3V3 + 0.3
adc_high ADC and DAC reference voltage (high) analog input -0.5 VDD3V3 + 0.5
adc_low ADC and DAC reference voltage (low) analog input -0.5 VDD3V3 + 0.5
adc0_in ADC0 analog input analog input -0.5 VDD3V3 + 0.5
adc1_in ADC1 analog input analog input -0.5 VDD3V3 + 0.5
comp_inn Comparator negative input analog input -0.5 VDD3V3 + 0.5
comp_inp Comparator positive input analog input -0.5 VDD3V3 + 0.5
analog_out DAC and bandgap analog output analog output 0.0 VDD3V3
VDD1V8 Core Analog/Digital voltage (output) power inout 1.5 2.1
VDD3V3 Common Analog/Digital power supply power inout 3.6 3.0
GND Common Analog/Digital Ground ground inout 0 0

Parameters

Global Conditions

NAME MINIMUM TYPICAL MAXIMUM UNITS
VDD3V3 3.3 V
Ground 0 V
Corner tm
Sigma 3

Electrical Parameters

PARAMETER PIN MINIMUM TYPICAL MAXIMUM UNITS

Physical Parameters

PARAMETER MINIMUM TYPICAL MAXIMUM UNITS
device_area µm²
area µm²
width µm
height µm
DRC_errors
LVS_errors