DESIGN MARKETPLACE
SoC Platform
Description:
This contains a sample user project that utilizes the caravel chip user space.
Features:
- SKY130 Open PDK
- 37 programable IO's
- 10 sq mm user design space
- IP Type: Soft IP
- Category: N/A
- Vendor: Efabless
- Node: 130nm
- Foundry: Skywater
- Process: ['sky130A']
- Designer: Efabless engineering License:
- Contact Designer
- Stage: Schematic
-
Certifications:
Description:
Cortex M0 design for embedded controllers and intelligent sensors.
Features:
- SoC Design Template Cortex M0 CPU Core
- AHB-Lite and APB buses
- Up to 32 APB peripherals
- Up to 8 AHB peripherals
- Analog peripheral options include: ADC
- Digital peripheral options include: SPI, GPIO, I2C, UART, PWM/Timer
- 8, 16 or 32kB internal SRAM memory
- QSPI XIP memory controller for booting and executing from external serial Flash memory
- IP Type:
- Category: N/A
- Vendor: Efabless
- Node: 130nm
- Foundry: GlobalFoundries
- Process: ['GF013GA', 'GF013GB', 'GF013GC', 'GF013GD', 'GF013GE']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Schematic
-
Certifications:
Description:
Hydra v2p0 demonstration chip
Features:
- 5 bandgap references
- SPI controller
- On-board ADC
- Crystal oscillator
- IP Type: Hard IP
- Category: N/A
- Vendor: efabless
- Node: 350nm
- Foundry: N/A
- Process: ['EFXH035B']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Prototype
-
Certifications:
Description:
Full chip implementation of the KZOA0351IP operational amplifier
Features:
- High bandwidth
- Low offset
- High CMRR
- Low power consumption
- IP Type: Hard IP
- Category: N/A
- Vendor: community
- Node: 350nm
- Foundry: N/A
- Process: ['EFXH035B']
- Designer: Khaled Zaki Ahmed Hussein License:
- Contact Designer
- Stage: Layout
- Certifications:
Description:
Cortex M0 design for embedded controllers and intelligent sensors.
Features:
- SoC Design Template Cortex M0 CPU Core
- AHB-Lite and APB buses
- Up to 32 APB peripherals
- Up to 8 AHB peripherals
- Analog peripheral options include: ADC, DAC, Comparator
- Digital peripheral options include: SPI, GPIO, I2C, UART, PWM/Timer
- 8, 16 or 32kB internal SRAM memory
- QSPI XIP memory controller for booting and executing from external serial Flash memory
- IP Type: Soft IP
- Category: N/A
- Vendor: efabless
- Node: 180nm
- Foundry: X-FAB
- Process: ['EFXH018D']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Silicon
-
Certifications:
Description:
SIP design for IoT using a Cortex M0 with BLE and Flash dies.
Features:
- Raptor SoC Design Template Cortex M0 CPU Core
- AHB-Lite and APB buses
- Up to 32 APB peripherals
- Up to 8 AHB peripherals
- Analog peripheral options include: ADC, DAC, Comparator
- Digital peripheral options include: SPI, GPIO, I2C, UART, PWM/Timer
- 8, 16 or 32kB internal SRAM memory
- QSPI XIP memory controller for booting and executing from external serial Flash memory
- IP Type: Soft IP
- Category: N/A
- Vendor: efabless
- Node: 180nm
- Foundry: X-FAB
- Process: ['EFXH018D']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Layout
-
Certifications:
Description:
Full-chip reference implementation of the PicoRV32 PicoSoc in X-Fab XH018.
Features:
- 100 MHz clock rate
- Selectable clock source
- 16 channels GPIO
- 2 ADCs
- 1 DAC
- 1 Comparator
- Over-temperature alarm
- 100 kHz RC oscillator
- Selectable functions on GPIO outputs
- Selectable interrupts on GPIO inputs
- IP Type: Hard IP
- Category: N/A
- Vendor: efabless
- Node: 180nm
- Foundry: N/A
- Process: ['EFXH018D']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Silicon
- Certifications:
Description:
Embedded controller RISC-V reference design based on PicoRV32 with NVRAM.
Features:
- 8kB memory
- 512 bits non-volatile memory
- 2 10-bit ADCs
- 1 10-bit DAC
- I2C controller
- QSPI flash controller
- UART
- IP Type: Hard IP
- Category: N/A
- Vendor: efabless
- Node: 180nm
- Foundry: X-FAB
- Process: ['EFXH018D']
- Designer: efabless engineering License:
- Contact Designer
- Stage: Layout
- Certifications:
